Nexperia 2 Flip Flop IC 74LVC, D Type, 14-Pin TSSOP
- RS Stock No.:
- 170-5415P
- Mfr. Part No.:
- 74LVC74APW,118
- Brand:
- Nexperia
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In Stock
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Units | Per unit |
|---|---|
| 150 - 250 | £0.08 |
| 300 - 550 | £0.078 |
| 600 - 1200 | £0.076 |
| 1250 + | £0.074 |
*price indicative
- RS Stock No.:
- 170-5415P
- Mfr. Part No.:
- 74LVC74APW,118
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | D Type | |
| Clock Frequency | 120MHz | |
| Polarity | Inverting, Non-Inverting | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 1.65V | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 14 | |
| Flip-Flop Type | D Flip-Flop | |
| Maximum Propagation Delay Time @ CL | 6.5ns | |
| Minimum Operating Temperature | -40°C | |
| Trigger Type | Positive Edge | |
| Maximum Operating Temperature | 125°C | |
| Number of Elements per Chip | 2 | |
| Standards/Approvals | No | |
| Length | 5.1mm | |
| Height | 0.95mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74LVC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type D Type | ||
Clock Frequency 120MHz | ||
Polarity Inverting, Non-Inverting | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 1.65V | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 14 | ||
Flip-Flop Type D Flip-Flop | ||
Maximum Propagation Delay Time @ CL 6.5ns | ||
Minimum Operating Temperature -40°C | ||
Trigger Type Positive Edge | ||
Maximum Operating Temperature 125°C | ||
Number of Elements per Chip 2 | ||
Standards/Approvals No | ||
Length 5.1mm | ||
Height 0.95mm | ||
Automotive Standard No | ||
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous Active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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