Winbond W9751G6NB25I, SDRAM 512Mbit Surface Mount, 400MHz, 1.7 V to 1.9 V, 84-Pin VFBGA
- RS Stock No.:
- 242-0781P
- Mfr. Part No.:
- W9751G6NB25I
- Brand:
- Winbond
Bulk discount available
Subtotal 10 units (supplied in a tray)*
£24.70
(exc. VAT)
£29.60
(inc. VAT)
FREE delivery for orders over £50.00
In Stock
- 56 unit(s) ready to ship
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit |
|---|---|
| 10 - 18 | £2.47 |
| 20 - 48 | £2.405 |
| 50 - 98 | £2.345 |
| 100 + | £2.285 |
*price indicative
- RS Stock No.:
- 242-0781P
- Mfr. Part No.:
- W9751G6NB25I
- Brand:
- Winbond
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Winbond | |
| Memory Size | 512Mbit | |
| SDRAM Class | DDR2 | |
| Organisation | 32Mx16 | |
| Data Rate | 400MHz | |
| Data Bus Width | 16bit | |
| Address Bus Width | 15bit | |
| Number of Bits per Word | 16bit | |
| Maximum Random Access Time | 0.4ns | |
| Number of Words | 32M | |
| Mounting Type | Surface Mount | |
| Package Type | VFBGA | |
| Pin Count | 84 | |
| Height | 0.6mm | |
| Length | 12.5mm | |
| Minimum Operating Supply Voltage | 1.7 V | |
| Maximum Operating Supply Voltage | 1.9 V | |
| Maximum Operating Temperature | +95 °C | |
| Width | 8mm | |
| Minimum Operating Temperature | -40 °C | |
| Select all | ||
|---|---|---|
Brand Winbond | ||
Memory Size 512Mbit | ||
SDRAM Class DDR2 | ||
Organisation 32Mx16 | ||
Data Rate 400MHz | ||
Data Bus Width 16bit | ||
Address Bus Width 15bit | ||
Number of Bits per Word 16bit | ||
Maximum Random Access Time 0.4ns | ||
Number of Words 32M | ||
Mounting Type Surface Mount | ||
Package Type VFBGA | ||
Pin Count 84 | ||
Height 0.6mm | ||
Length 12.5mm | ||
Minimum Operating Supply Voltage 1.7 V | ||
Maximum Operating Supply Voltage 1.9 V | ||
Maximum Operating Temperature +95 °C | ||
Width 8mm | ||
Minimum Operating Temperature -40 °C | ||
The Winbond SDRAM is a 512M bits DDR2 SDRAM which is organized as 8,388,608 words, 4 banks, 16 bits. This device achieves high speed transfer rates for various applications.
Two data transfers per clock cycle
Edge-aligned with read data and centre-aligned with write data
DLL aligns DQ and DQS transitions with clock
Edge-aligned with read data and centre-aligned with write data
DLL aligns DQ and DQS transitions with clock