The Microchip dsPIC30F6014A series have a modified Harvard architecture, a C compiler optimized instruction set architecture and flexible addressing modes. The device is able to perform dual data fetch modulo and bit-reversed modes. The devices CMOS technology offers low-power, high-speed flash operations. It has industrial and extended temperature ranges and low power consumption . The Fail-safe clock monitor operation detects clock failure and switches to on-chip low-power RC oscillator. The device offers programmable code protection and In-circuit serial programming (ICSP) and also selectable power management modes which are sleep, Idle and alternate clock modes.

Wide operating voltage range from 2.5V to 5.5V
Program memory of 144K Bytes
SRAM of 8192 Bytes
EEPROM of 4096 Bytes
It has five 16-bit timers/counters
High-current sink and source of 25 mA on Input and Output pins