The Renesas Electronics clock buffer is a high-speed phase-lock loop (PLL) ,designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz.

The clock buffer is an 8-pin version of the IDT23S09E
The -1H version operates up to 200MHz frequency and has a higher drive than the -1 device
All parts have on-chip PLLs which lock to an input clock on the REF pin
The PLL feedback is on-chip and is obtained from the CLKOUT pad
Operating frequency of 10MHz to 200MHz
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Low jitter of less than 200 ps cycle-to-cycle
No external RC network required
Power down mode
Spread spectrum compatible
Available in SOIC package