The Renesas Electronics zero delay clock buffer is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, it enters power down.

Distributes one clock input to one bank of five outputs
Zero input-output delay
Output skew < 250ps
Low jitter <200 ps cycle-to-cycle
No external RC network required