Core: Arm^® 32-bit Cortex^®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions

Operating conditions:

• V_DD, V_DDA voltage range: 1.71 V to 3.6 V

Mathematical hardware accelerators

• CORDIC for trigonometric functions acceleration
• FMAC: filter mathematical accelerator

Memories

• 512 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP
• 96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes
• Routine booster: 16 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)
• Quad-SPI memory interface

Reset and supply management

• Power-on/power-down reset (POR/PDR/BOR)
• Programmable voltage detector (PVD)
• Low-power modes: sleep, stop, standby and shutdown
• V_BAT supply for RTC and backup registers

Clock management

• 4 to 48 MHz crystal oscillator
• 32 kHz oscillator with calibration
• Internal 16 MHz RC with PLL option (± 1%)
• Internal 32 kHz RC oscillator (± 5%)

Up to 86 fast I/Os

• All mappable on external interrupt vectors
• Several I/Os with 5 V tolerant capability

Interconnect matrix

16-channel DMA controller

3 x ADCs 0.25 µs (up to 36 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range

4 x 12-bit DAC channels

• 2 x buffered external channels 1 MSPS
• 2 x unbuffered internal channels 15 MSPS

4 x ultra-fast rail-to-rail analog comparators

4 x operational amplifiers that can be used in PGA mode, all terminals accessible

Internal voltage reference