High Performance RISC CPU:
C Compiler optimized architecture/instruction set
Data EEPROM to 1024 bytes
Linear program memory addressing to 64 Kbytes
Linear data memory addressing to 4 Kbytes
Up to 16 MIPS operation
16-bit wide instructions, 8-bit wide data path
Priority levels for interrupts
31-level, software accessible hardware stack
8 x 8 Single-Cycle Hardware Multiplier
Extreme Low-Power Management with nanoWatt XLP™:
Sleep mode: 100 nA, typical
Watchdog Timer: 500 nA, typical
Timer1 Oscillator: 500 nA @ typical 32 kHz
Flexible Oscillator Structure:
Precision 16 MHz internal oscillator block:
Factory calibrated to ± 1%
Software selectable frequencies range of 31 kHz to 16 MHz
64 MHz performance available using PLL
no external components required
Four Crystal modes up to 64 MHz
Two external Clock modes up to 64 MHz
4X Phase Lock Loop (PLL)
Secondary oscillator using Timer1 @ 32 kHz