AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions.
To fully exploit the power of a 32-bit architecture, the AVR32 is not binary compatible with earlier AVR architectures. In order to achieve high code density, the instruction format is flexible providing both compact 16-bit and extended 32-bit instructions. While most instructions are 16-bit, powerful 32-bit instructions are implemented to further increase performance. Compact and extended instructions can be freely mixed in the instruction stream.

The Microchip AT32UC3C 32-bit System-On-Chip microcontroller is based on the AVR32UC RISC processor running at frequencies up to 66 MHz. It operates on single 3.3V or 5V power supply. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. It incorporates on-chip Flash and SRAM memories for secure and fast access. The Memory Direct Memory Access controller (MDMA) enables transfers of block of data from memories to memories without processor involvement. The Peripheral Direct Memory Access (PDCA) controller enables data transfers between peripherals and memories without processor involvement, also drastically reduces processing overhead when transferring continuous and large data streams. It features many communication interfaces for communication intensive applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like flexible CAN, USB and Ethernet MAC are available. The USART supports different communication modes, like SPI mode and LIN mode.

Performing 1.49 DMIPS / MHz
Memory Protection Unit
Maximum CPU speed of 66MHz
High-Performance Data Transfers on Separate Buses for Increased Performance
Flash Security Locks and User Defined Configuration Area
Internal High-Speed flash of 512 Kbytes
Internal High-Speed SRAM of 64 Kbytes
Auto vectored Low Latency Interrupt Service with Programmable Priority
Windowed Watchdog Timer (WDT)
Asynchronous Timer (AST) with Real-Time Clock Capability
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Supports Media Independent Interface (MII) and Reduced MII (RMII)
One 4-Channel 20-bit Pulse Width Modulation Controller (PWM)
One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC)
Package type of 64-pin QFN/TQFP (45 GPIO pins)