The STM32756G-EVAL2 Evaluation Board is a complete demonstration and development platform for the STMicroelectronics STM32F756NGH6 microcontroller, based on the high-performance ARM® Cortex®-M7 32-bit core with internal 1Mbytes Flash and 320Kbytes + 4Kbytes of backup SRAM.
It features four I²C interfaces, six SPIs with three mutiplexed simplex I²S interfaces, SDMMC, four USARTs, two CANs, three 12-bit ADCs, two 12-bit DACs, two SAIs, 8- to 14-bit digital camera module interface, USB OTG HS and USB OTG FS, Ethernet MAC, FMC interface, Quad-SPI interface, Cryptographic acceleration, JTAG debugging support.
The full range of hardware features on the board helps the user to evaluate all peripherals.

Six 5V power supply options: External power connector, ST-LINK/V2-1 USB, USB HS, USB FS1, USB FS2 connectors, and daughterboard
Serial Audio Interfaces (SAI) DAC, stereo audio jack which supports headset with microphone
Stereo digital microphone, audio jack connector used to connect external speakers
2Gbytes (or more) SDMMC interface microSD card
13.56MHz RF-EEPROM M24LR64-R on I²C compatible serial interface
RS-232 serial communication
IrDA transceiver
JTAG/SWD and ETM trace debug support, ST-LINK/V2-1 embedded
IEEE-802.3-2002 compliant Ethernet connector
Camera module
8Mx32-bit SDRAM, 1Mx16-bit SRAM & 8Mx16-bit NOR Flash
512Mbits QuadSPI NOR Flash
5.7 inch 640x480 pixel TFT colour LCD with capacitive touch panel
Joystick with 4-direction control and selector button
Reset, WakeUp/Tamper or key button
4 colour user LEDs
Extension connectors & memory connectors for daughterboard or wrapping board
USB OTG HS and FS with Micro-AB connectors
Real-Time-Clock (RTC) with backup battery
CAN 2.0 A/B compliant connection
Potentiometer
Motor control connector

The STM32F7 microcontrollers feature ST’s ART Accelerator™ as well as an L1 cache and deliver the maximum theoretical performance of the ARM Cortex-M7 core, regardless if code is executed from embedded Flash or external memory. Typical performance figures: 1082 CoreMark / 462 DMIPS at 216MHz clock frequency.

AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
Double-Precision Floating-Point maths unit on some variants
Up to 16KB +16KB of I-cache and D-cache
Up to 2MB of embedded Flash memory, with Read-While-Write capability on certain devices
Up to 512KB of data memory, including up to 128KB of Tightly-Coupled Memory for Data (DTCM) for Stacks, Heaps
16KB of Tightly-Coupled Memory for Instructions (ITCM) for time-critical routines
4KB of backup SRAM to keep data in the lowest power modes
Peripheral speed is independent from CPU speed (dual clock support)
Protected code execution feature (PC-ROP) on some variants
Power Efficiency: 7 CoreMark/mW at +1.8Vdc