Nexperia 74HC73D-Q100J Flip Flop IC HC, CMOS, 14-Pin SO-14
- RS Stock No.:
- 243-4416
- Mfr. Part No.:
- 74HC73D-Q100J
- Brand:
- Nexperia
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In Stock
- 1,100 unit(s) ready to ship
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Units | Per unit | Per Pack* |
|---|---|---|
| 25 - 25 | £0.293 | £7.33 |
| 50 - 75 | £0.287 | £7.18 |
| 100 - 225 | £0.225 | £5.63 |
| 250 - 975 | £0.21 | £5.25 |
| 1000 + | £0.142 | £3.55 |
*price indicative
- RS Stock No.:
- 243-4416
- Mfr. Part No.:
- 74HC73D-Q100J
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | HC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | CMOS | |
| Polarity | Negative | |
| Mount Type | Surface | |
| Package Type | SO-14 | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 6V | |
| Pin Count | 14 | |
| Trigger Type | Negative Edge | |
| Minimum Operating Temperature | -40°C | |
| Flip-Flop Type | JK Type | |
| Maximum Operating Temperature | 125°C | |
| Series | 74HC73-Q100 | |
| Standards/Approvals | HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | |
| Automotive Standard | AEC-Q100 Grade 1 | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family HC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type CMOS | ||
Polarity Negative | ||
Mount Type Surface | ||
Package Type SO-14 | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 6V | ||
Pin Count 14 | ||
Trigger Type Negative Edge | ||
Minimum Operating Temperature -40°C | ||
Flip-Flop Type JK Type | ||
Maximum Operating Temperature 125°C | ||
Series 74HC73-Q100 | ||
Standards/Approvals HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | ||
Automotive Standard AEC-Q100 Grade 1 | ||
The Nexperia dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output high. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
CMOS low-power dissipation
Wide supply voltage range from 2.0 to 6.0 V
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
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