Renesas Electronics 9FGV0441AKILF, PLL Clock Generator 32-Pin VFQFPN
- RS Stock No.:
- 262-9024
- Mfr. Part No.:
- 9FGV0441AKILF
- Brand:
- Renesas Electronics
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Subtotal (1 pack of 2 units)*
£6.71
(exc. VAT)
£8.052
(inc. VAT)
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In Stock
- 980 unit(s) ready to ship
- Plus 999,999,018 unit(s) shipping from 20 January 2026
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Units | Per unit | Per Pack* |
---|---|---|
2 - 8 | £3.355 | £6.71 |
10 - 18 | £3.005 | £6.01 |
20 - 98 | £2.945 | £5.89 |
100 - 198 | £2.46 | £4.92 |
200 + | £2.415 | £4.83 |
*price indicative
- RS Stock No.:
- 262-9024
- Mfr. Part No.:
- 9FGV0441AKILF
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Renesas Electronics | |
Package Type | VFQFPN | |
Pin Count | 32 | |
Select all | ||
---|---|---|
Brand Renesas Electronics | ||
Package Type VFQFPN | ||
Pin Count 32 | ||
- COO (Country of Origin):
- MY
The Renesas Electronics PCIE GEN123 CLK GEN is an 4-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo = 100Ω. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.
Integrated terminations provide 100Ω differential Zo reduced component count and board space
1.8V operation reduced power consumption
OE pins support DIF power management
LP-HCSL differential clock outputs reduced power and board space
Programmable slew rate for each output allows tuning for various line lengths
Programmable output amplitude allows tuning for various application environments
DIF outputs blocked until PLL is locked clean system start-up
1.8V operation reduced power consumption
OE pins support DIF power management
LP-HCSL differential clock outputs reduced power and board space
Programmable slew rate for each output allows tuning for various line lengths
Programmable output amplitude allows tuning for various application environments
DIF outputs blocked until PLL is locked clean system start-up
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