85102AGILF, Clock Buffer, 5-Input, 16-Pin TSSOP
- RS Stock No.:
- 216-6208
- Mfr. Part No.:
- 85102AGILF
- Brand:
- Renesas Electronics
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Subtotal (1 unit)*
£12.03
(exc. VAT)
£14.44
(inc. VAT)
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Last RS stock
- Final 72 unit(s), ready to ship
Units | Per unit |
|---|---|
| 1 - 9 | £12.03 |
| 10 - 24 | £11.07 |
| 25 - 49 | £10.61 |
| 50 - 99 | £10.20 |
| 100 + | £9.35 |
*price indicative
- RS Stock No.:
- 216-6208
- Mfr. Part No.:
- 85102AGILF
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Function | Clock Buffer | |
| Number of Clock Inputs | 5 | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Function Clock Buffer | ||
Number of Clock Inputs 5 | ||
Package Type TSSOP | ||
Pin Count 16 | ||
The Renesas Electronics 85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The 85102I has a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well defi ned performance and repeatability.
Two 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)