Infineon Clock Buffer 8-Pin SOIC
- RS Stock No.:
- 273-7329
- Mfr. Part No.:
- CY2305SXI-1H
- Brand:
- Infineon
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Units | Per unit |
|---|---|
| 1 - 9 | £2.85 |
| 10 - 24 | £2.49 |
| 25 - 49 | £2.45 |
| 50 - 99 | £2.39 |
| 100 + | £2.11 |
*price indicative
- RS Stock No.:
- 273-7329
- Mfr. Part No.:
- CY2305SXI-1H
- Brand:
- Infineon
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Infineon | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Maximum Propagation Delay Time | 8.7ns | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 8 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Standards/Approvals | No | |
| Length | 5.84mm | |
| Width | 4.8 mm | |
| Series | CY2305 | |
| Height | 1.5mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Infineon | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Maximum Propagation Delay Time 8.7ns | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 8 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Standards/Approvals No | ||
Length 5.84mm | ||
Width 4.8 mm | ||
Series CY2305 | ||
Height 1.5mm | ||
Automotive Standard No | ||
The Infineon Zero delay buffer designed to distribute high speed clocks. It accepts one reference input, and drives out five low skew clocks. All parts have on chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on chip and is obtained from the CLKOUT pad. This buffer devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.
60 ps typical cycle to cycle jitter
Zero input output propagation delay
Test mode to bypass phase locked loop
Compatible with Pentium based systems
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