The Infineon Zero delay buffer designed to distribute high speed clocks. It accepts one reference input and drives out five low skew clocks. All parts have on chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on chip and is obtained from the CLKOUT pad. This buffer devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.

60 ps typical cycle to cycle jitter
Zero input output propagation delay
Test mode to bypass phase locked loop
Compatible with Pentium based systems