The Infineon Zero delay buffer designed to distribute high speed clocks and is available in a 8 pin SOIC package. It accepts one reference input and drives out five low skew clocks. All parts have on chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on chip and is obtained from the CLKOUT pad.

Multiple low skew outputs
60 ps typical cycle to cycle jitter
Zero input output propagation delay
Compatible with Pentium based systems