The Renesas Electronics PLL clock is a zero delay buffer which supports PCI Express clocking requirements. It is driven by a differential SRC output pair from an ICS CK410 or CK505 compliant main clock. It attenuates jitter on the input clock and has a selectable PLL band width to maximize performance in systems with or without spread spectrum clocking.

PLL or bypass mode or PLL can dejitter incoming clock available
SMBus interface or unused outputs can be disabled
Industrial temperature range available
Spread Spectrum Compatible or tracks spreading input clock for low EMI