The Renesas Electronics high-performance LVCMOS clock buffer has an additive phase jitter of 50 fs RMS. There are five different fan-out variations available that is 1:2 to 1:10. Its supports a synchronous glitch-free output enable (OE) function to eliminate any potential intermediate incorrect output clock cycles when enabling or disabling outputs. It can operate from a 1.8 V to 3.3 V supply.

High-performance 1:2, 1:4, 1:6, 1:8, 1:10 LVCMOS clock buffer
Very low pin-to-pin skew: < 50 ps
Very low additive jitter: < 50 fs
Supply voltage: 1.8 V to 3.3 V
3.3 V tolerant input clock
fMAX is 200 MHz
Integrated serial termination for 50 Ω channel
Packaged in 8-, 14-, 16-, 20-pin TSSOP and as small as 2 x 2 mm DFN and 3 x 3 mm VFQFPN packages
Industrial (-40°C to +85°C) and extended (-40°C to +105°C) temperature ranges