The Renesas Electronics fan out buffer is of low skew, high performance 1 to 5 Differential to 2.5V/3.3V LVPECL .It has two selectable clock inputs. The CLK0,nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/desertion of the clock enable pin.

It has 5 differential 2.5 or 3.3V LVPECL outputs
Selectable differential CLK0/nCLK0 /LVCMOS inputs provided
Maximum output frequency is 700MHz
Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
Maximum part to part skew is 350ps
It has maximum propagation delay of 1.8ns
RMS phase jitter of 155.52MHz
Ambient operating temperature is -40°C to 85°C