The Renesas Electronics fan out buffer is of low skew, high performance 1 to 4 LVCMOS/LVTTL to 3.3V LVPECL . It has two single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input level and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/desertion of the clock enable pin.

It provides four differential 3.3V LVPECL outputs
The buffer has selectable CLK0 or CLK1 inputs for redundant and multiple frequency fan out applications
CLK0 or CLK1 can accept two input levels that are LVCMOS or LVTTL
Maximum output frequency is 266MHz
Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
Maximum output skew is 30ps
Maximum part-to-part skew is 250ps
It has maximum propagation delay of 1.9ns
Ambient operating temperature is -40°C to 85°C