The Renesas Electronics high performance zero delay buffer which integrates IDTs proprietary analog or digital phase locked loop techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs. The chip is part of IDTs clockBlocksTM family, and was designed as a performance upgrade to meet todays higher speed and lower voltage requirements.

Eight pin soic package
Passes spread spectrum clock modulation
Full cmos clock swings with 25 ma drive capability at ttl levels
Advanced, low power cmos process
Industrial temperature version available