The Renesas Electronics high speed phase lock loop clock buffer, designed to address high speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.The IDT2305 is an eight pin version of the IDT2309. IDT2305 accepts one reference input, and drives out five low skew clocks.

Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
Zero input output delay
No external rc network required
Available in soic and tssop packages