Renesas Electronics 2305-1DCGI8 Clock Buffer 8-Pin SOIC/TSSOP
- RS Stock No.:
- 235-8695P
- Mfr. Part No.:
- 2305-1DCGI8
- Brand:
- Renesas Electronics
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Subtotal 50 units (supplied on a continuous strip)*
£22.80
(exc. VAT)
£27.35
(inc. VAT)
FREE delivery for orders over £50.00
In Stock
- 1,530 unit(s) ready to ship
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Units | Per unit |
---|---|
50 - 90 | £0.456 |
100 - 240 | £0.374 |
250 - 990 | £0.351 |
1000 + | £0.309 |
*price indicative
- RS Stock No.:
- 235-8695P
- Mfr. Part No.:
- 2305-1DCGI8
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Renesas Electronics | |
Maximum Supply Current | 32 mA | |
Mounting Type | Surface Mount | |
Package Type | SOIC/TSSOP | |
Pin Count | 8 | |
Dimensions | 4.90 x 3.90 x 1.50mm | |
Length | 4.9mm | |
Width | 3.9mm | |
Height | 1.5mm | |
Maximum Operating Supply Voltage | 3.6 V | |
Maximum Operating Temperature | 85 °C | |
Maximum Output Frequency | 133MHz | |
Minimum Operating Supply Voltage | 3 V | |
Minimum Output Frequency | 10MHz | |
Minimum Operating Temperature | -40 °C | |
Select all | ||
---|---|---|
Brand Renesas Electronics | ||
Maximum Supply Current 32 mA | ||
Mounting Type Surface Mount | ||
Package Type SOIC/TSSOP | ||
Pin Count 8 | ||
Dimensions 4.90 x 3.90 x 1.50mm | ||
Length 4.9mm | ||
Width 3.9mm | ||
Height 1.5mm | ||
Maximum Operating Supply Voltage 3.6 V | ||
Maximum Operating Temperature 85 °C | ||
Maximum Output Frequency 133MHz | ||
Minimum Operating Supply Voltage 3 V | ||
Minimum Output Frequency 10MHz | ||
Minimum Operating Temperature -40 °C | ||
The Renesas Electronics high speed phase lock loop clock buffer, designed to address high speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.The IDT2305 is an eight pin version of the IDT2309. IDT2305 accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
Zero input output delay
No external rc network required
Available in soic and tssop packages
Distributes one clock input to one bank of five outputs
Zero input output delay
No external rc network required
Available in soic and tssop packages