These dual P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS.

-25 V, -0.41 A continuous, -1.5 A Peak.
RDS(ON) = 1.1 Ω @ VGS= -4.5 V,
RDS(ON) = 1.5 Ω @ VGS= -2.7 V.
Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) <1.5 V).
Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).
Compact industry standard SC70-6 surface mount package.
Applications
This product is general usage and suitable for many different applications.