These dual N & P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.

N-Ch
0.50 A, 25 V
RDS(ON) = 0.45 Ω @ VGS= 4.5 V
RDS(ON) = 0.60 Ω @ VGS= 2.7 V
P-Ch
-0.41 A, -25 V
RDS(ON) = 1.1 Ω @ VGS= -4.5 V
RDS(ON) = 1.5 Ω @ VGS= -2.7 V
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).
Applications
This product is general usage and suitable for many different applications.