The Renesas Electronics CMOS SRAM is organized as 2K x 8. The SRAM offers a reduced power standby mode. The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.

Low-power consumption
Battery backup operation 2V data retention voltage
Produced with advanced CMOS high-performance technology
CMOS process virtually eliminates alpha particle soft-error rates
Input and output directly TTL-compatible
No clocks or refresh required