Infineon S27KL0642DPBHI020, SDRAM 64Mbit, 400Mbps, 24-Pin 24-ball FBGA
- RS Stock No.:
- 273-7512
- Mfr. Part No.:
- S27KL0642DPBHI020
- Brand:
- Infineon
Bulk discount available
Subtotal (1 tray of 338 units)*
£730.08
(exc. VAT)
£875.42
(inc. VAT)
FREE delivery for orders over £50.00
Temporarily out of stock
- Shipping from 26 December 2025
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Tray* |
---|---|---|
338 - 676 | £2.16 | £730.08 |
1014 + | £2.053 | £693.91 |
*price indicative
- RS Stock No.:
- 273-7512
- Mfr. Part No.:
- S27KL0642DPBHI020
- Brand:
- Infineon
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Infineon | |
Memory Size | 64Mbit | |
SDRAM Class | DDR | |
Data Rate | 400Mbps | |
Data Bus Width | 8bit | |
Package Type | 24-ball FBGA | |
Pin Count | 24 | |
Select all | ||
---|---|---|
Brand Infineon | ||
Memory Size 64Mbit | ||
SDRAM Class DDR | ||
Data Rate 400Mbps | ||
Data Bus Width 8bit | ||
Package Type 24-ball FBGA | ||
Pin Count 24 | ||
The Infineon DRAM is a high speed CMOS, self refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM.
200 MHz maximum clock rate
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock
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