The Infineon DRAM is a high speed CMOS, self refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM.

200 MHz maximum clock rate
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock