Alliance Memory SDRAM 128 MB Surface, 54-Pin 16 bit TSOP
- RS Stock No.:
- 230-8444P
- Mfr. Part No.:
- AS4C8M16SA-7TCNTR
- Brand:
- Alliance Memory
Bulk discount available
Subtotal 50 units (supplied on a continuous strip)*
£113.75
(exc. VAT)
£136.50
(inc. VAT)
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Units | Per unit |
|---|---|
| 50 - 98 | £2.275 |
| 100 - 248 | £2.045 |
| 250 - 498 | £2.04 |
| 500 + | £1.965 |
*price indicative
- RS Stock No.:
- 230-8444P
- Mfr. Part No.:
- AS4C8M16SA-7TCNTR
- Brand:
- Alliance Memory
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 128MB | |
| Data Bus Width | 16bit | |
| Address Bus Width | 121bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 166MHz | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 2M | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 70°C | |
| Series | AS4C8M16SA | |
| Standards/Approvals | No | |
| Length | 22.35mm | |
| Height | 1.2mm | |
| Minimum Supply Voltage | 3V | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 3.6V | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 128MB | ||
Data Bus Width 16bit | ||
Address Bus Width 121bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 166MHz | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 2M | ||
Mount Type Surface | ||
Package Type TSOP | ||
Minimum Operating Temperature 0°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 70°C | ||
Series AS4C8M16SA | ||
Standards/Approvals No | ||
Length 22.35mm | ||
Height 1.2mm | ||
Minimum Supply Voltage 3V | ||
Automotive Standard No | ||
Maximum Supply Voltage 3.6V | ||
The Alliance Memory 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL