Alliance Memory AS4C512M16D3LC-10BCN SDRAM 8 GB Surface, 96-Pin 16 bit FBGA-96 Ball
- RS Stock No.:
- 425-299
- Mfr. Part No.:
- AS4C512M16D3LC-10BCN
- Brand:
- Alliance Memory
Subtotal (1 tray of 190 units)*
£8,177.22
(exc. VAT)
£9,812.74
(inc. VAT)
Stock information currently inaccessible - Please check back later
Units | Per unit | Per Tray* |
|---|---|---|
| 190 + | £43.038 | £8,177.22 |
*price indicative
- RS Stock No.:
- 425-299
- Mfr. Part No.:
- AS4C512M16D3LC-10BCN
- Brand:
- Alliance Memory
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Memory Size | 8GB | |
| Product Type | SDRAM | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 933MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-96 Ball | |
| Pin Count | 96 | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 95°C | |
| Series | AS4C512M16D3LC | |
| Standards/Approvals | Industrial, automotive, Extended, Commercial | |
| Length | 13mm | |
| Height | 1.2mm | |
| Minimum Supply Voltage | 1.283V | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.35V | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Memory Size 8GB | ||
Product Type SDRAM | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 933MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-96 Ball | ||
Pin Count 96 | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 95°C | ||
Series AS4C512M16D3LC | ||
Standards/Approvals Industrial, automotive, Extended, Commercial | ||
Length 13mm | ||
Height 1.2mm | ||
Minimum Supply Voltage 1.283V | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.35V | ||
- COO (Country of Origin):
- TW
The Alliance Memory 8gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
RoHS compliant
Auto Refresh and Self Refresh
Related links
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