System developers designing high-end embedded control applications can benefit from a new Digital Signal Controller (DSC) with two dsPIC DSC cores in a single chip. The dsPIC33CH has one core that is designed to function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions, customized for the end application.

Operating Conditions
3V to 3.6V, -40°C to +125°C
Core: Dual 16-Bit dsPIC33CH CPUs
Master Core 90 MIPS and Slave Core 100 MIPS Operation
Independent Peripherals for Master Core and Slave Core
Configurable Shared Resources for Master Core and Slave Core
Programmable PLLs and Oscillator Clock Sources
Fast Wake-up and Start-up
Backup Internal Oscillator
Low-Power Management Modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
Debugger Development Support