Microchip ATXMEGA64A3U-AU, 64bit AVR Microcontroller, ATxmega, 32MHz, 68 kB Flash, 64-Pin TQFP
- RS Stock No.:
- 899-6928
- Mfr. Part No.:
- ATXMEGA64A3U-AU
- Brand:
- Microchip
Stock information currently inaccessible
- RS Stock No.:
- 899-6928
- Mfr. Part No.:
- ATXMEGA64A3U-AU
- Brand:
- Microchip
Specifications
Technical Reference
Legislation and Compliance
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Family Name | ATxmega | |
| Package Type | TQFP | |
| Mounting Type | Surface Mount | |
| Pin Count | 64 | |
| Device Core | AVR | |
| Data Bus Width | 64bit | |
| Program Memory Size | 68 kB | |
| Maximum Frequency | 32MHz | |
| RAM Size | 4 kB | |
| USB Channels | 1 | |
| Number of PWM Units | 7 | |
| Typical Operating Supply Voltage | 1.6 → 3.6 V | |
| Width | 14.1mm | |
| Dimensions | 14.1 x 14.1 x 1.05mm | |
| Pulse Width Modulation | 7 (22 x 16 bit) | |
| Program Memory Type | Flash | |
| Data Rate | 115.2kbps | |
| Maximum Operating Temperature | +85 °C | |
| Number of ADC Units | 2 | |
| Length | 14.1mm | |
| ADCs | 2 (16 x 12 bit) | |
| Height | 1.05mm | |
| Maximum Number of Ethernet Channels | 0 | |
| Minimum Operating Temperature | -40 °C | |
| Instruction Set Architecture | RISC | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Family Name ATxmega | ||
Package Type TQFP | ||
Mounting Type Surface Mount | ||
Pin Count 64 | ||
Device Core AVR | ||
Data Bus Width 64bit | ||
Program Memory Size 68 kB | ||
Maximum Frequency 32MHz | ||
RAM Size 4 kB | ||
USB Channels 1 | ||
Number of PWM Units 7 | ||
Typical Operating Supply Voltage 1.6 → 3.6 V | ||
Width 14.1mm | ||
Dimensions 14.1 x 14.1 x 1.05mm | ||
Pulse Width Modulation 7 (22 x 16 bit) | ||
Program Memory Type Flash | ||
Data Rate 115.2kbps | ||
Maximum Operating Temperature +85 °C | ||
Number of ADC Units 2 | ||
Length 14.1mm | ||
ADCs 2 (16 x 12 bit) | ||
Height 1.05mm | ||
Maximum Number of Ethernet Channels 0 | ||
Minimum Operating Temperature -40 °C | ||
Instruction Set Architecture RISC | ||
