Silicon Labs, 32 bit ARM Cortex M4, EFM32 Microcontroller, 48 MHz, 256kB FLASH, 100-Pin LQFP
- RS Stock No.:
- 198-4611P
- Mfr. Part No.:
- EFM32WG880F256-B-QFP100
- Brand:
- Silicon Labs
Subtotal 10 units (supplied in a tray)*
£64.75
(exc. VAT)
£77.70
(inc. VAT)
FREE delivery for orders over £50.00
- Shipping from 20 October 2026
Units | Per unit |
|---|---|
| 10 - 18 | £6.475 |
| 20 - 48 | £6.305 |
| 50 - 98 | £6.14 |
| 100 + | £5.99 |
*price indicative
- RS Stock No.:
- 198-4611P
- Mfr. Part No.:
- EFM32WG880F256-B-QFP100
- Brand:
- Silicon Labs
Select all | Attribute | Value |
|---|---|---|
| Brand | Silicon Labs | |
| Series | EFM32 | |
| Product Type | Microcontroller | |
| Package Type | LQFP | |
| Mount Type | Surface | |
| Pin Count | 100 | |
| Device Core | ARM Cortex M4 | |
| Data Bus Width | 32bit | |
| Program Memory Size | 256kB | |
| Maximum Clock Frequency | 48MHz | |
| RAM Size | 32kB | |
| Maximum Supply Voltage | 3.8V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Number of Programmable I/Os | 93 | |
| Standards/Approvals | No | |
| DACs | 12 bit | |
| Analogue Comparators | 2 | |
| Minimum Supply Voltage | 1.98V | |
| ADCs | 12 x 12 Bit | |
| Program Memory Type | FLASH | |
| Automotive Standard | No | |
| Number of Timers | 1 | |
| Instruction Set Architecture | RISC | |
| Select all | ||
|---|---|---|
Brand Silicon Labs | ||
Series EFM32 | ||
Product Type Microcontroller | ||
Package Type LQFP | ||
Mount Type Surface | ||
Pin Count 100 | ||
Device Core ARM Cortex M4 | ||
Data Bus Width 32bit | ||
Program Memory Size 256kB | ||
Maximum Clock Frequency 48MHz | ||
RAM Size 32kB | ||
Maximum Supply Voltage 3.8V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Number of Programmable I/Os 93 | ||
Standards/Approvals No | ||
DACs 12 bit | ||
Analogue Comparators 2 | ||
Minimum Supply Voltage 1.98V | ||
ADCs 12 x 12 Bit | ||
Program Memory Type FLASH | ||
Automotive Standard No | ||
Number of Timers 1 | ||
Instruction Set Architecture RISC | ||
