Lapis, 16bit, ML62Q1200A Microcontroller, 32.76kHz, 16 kB Flash, 20-Pin TSSOP
- RS Stock No.:
- 180-8485
- Mfr. Part No.:
- ML62Q1233A-NNNTD
- Brand:
- Lapis
Stock information currently inaccessible
- RS Stock No.:
- 180-8485
- Mfr. Part No.:
- ML62Q1233A-NNNTD
- Brand:
- Lapis
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Lapis | |
| Family Name | ML62Q1200A | |
| Package Type | TSSOP | |
| Mounting Type | Surface Mount | |
| Pin Count | 20 | |
| Data Bus Width | 16bit | |
| Program Memory Size | 16 kB | |
| Maximum Frequency | 32.76kHz | |
| RAM Size | 2 kB | |
| Number of I2C Channels | 2 | |
| Typical Operating Supply Voltage | 5.5 (Maximum) V | |
| Number of UART Channels | 2 | |
| Maximum Operating Temperature | +105 °C | |
| Program Memory Type | Flash | |
| Number of ADC Units | 1 | |
| Minimum Operating Temperature | -40 °C | |
| Dimensions | 6.5 x 4.4 x 0.9mm | |
| Height | 0.9mm | |
| Instruction Set Architecture | RISC | |
| Width | 4.4mm | |
| Data Rate | 2Mbit/s | |
| ADCs | 1 (8 x 10 bit) | |
| Length | 6.5mm | |
| Select all | ||
|---|---|---|
Brand Lapis | ||
Family Name ML62Q1200A | ||
Package Type TSSOP | ||
Mounting Type Surface Mount | ||
Pin Count 20 | ||
Data Bus Width 16bit | ||
Program Memory Size 16 kB | ||
Maximum Frequency 32.76kHz | ||
RAM Size 2 kB | ||
Number of I2C Channels 2 | ||
Typical Operating Supply Voltage 5.5 (Maximum) V | ||
Number of UART Channels 2 | ||
Maximum Operating Temperature +105 °C | ||
Program Memory Type Flash | ||
Number of ADC Units 1 | ||
Minimum Operating Temperature -40 °C | ||
Dimensions 6.5 x 4.4 x 0.9mm | ||
Height 0.9mm | ||
Instruction Set Architecture RISC | ||
Width 4.4mm | ||
Data Rate 2Mbit/s | ||
ADCs 1 (8 x 10 bit) | ||
Length 6.5mm | ||
- COO (Country of Origin):
- JP
16-bit RISC CPU (CPU name: nX-U16/100)
Instruction system: 16-bit length instruction
Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000)
ISP (In-System Programming) function built-in
Minimum instruction execution time
30.5 μs (at 32.768 KHz system clock)
62.5ns/41.6ns (at 16 MHz/24MHz system clock)
Instruction system: 16-bit length instruction
Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000)
ISP (In-System Programming) function built-in
Minimum instruction execution time
30.5 μs (at 32.768 KHz system clock)
62.5ns/41.6ns (at 16 MHz/24MHz system clock)