Microchip PIC32MM0256GPM064-I/MR, 32bit microAptiv UC 32 bit Microcontroller, PIC32, 25MHz, 256 kB Flash, 64-Pin QFN

Unavailable
RS will no longer stock this product.
RS Stock No.:
146-3269
Mfr. Part No.:
PIC32MM0256GPM064-I/MR
Brand:
Microchip
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Brand

Microchip

Family Name

PIC32

Package Type

QFN

Mounting Type

Surface Mount

Pin Count

64

Device Core

microAptiv UC 32 bit

Data Bus Width

32bit

Program Memory Size

256 kB

Maximum Frequency

25MHz

RAM Size

32 kB

USB Channels

0

Number of PWM Units

1

Number of SPI Channels

3

Number of USART Channels

0

Number of UART Channels

3

Typical Operating Supply Voltage

2 → 3.6 V

Number of I2C Channels

3

Number of CAN Channels

0

Number of PCI Channels

0

Maximum Operating Temperature

+105 °C

Instruction Set Architecture

RISC

Number of ADC Units

1

Minimum Operating Temperature

-40 °C

Maximum Number of Ethernet Channels

0

Dimensions

9 x 9 x 0.85mm

Data Rate

6.25Mbit/s

Width

9mm

Number of LIN Channels

3

Height

0.85mm

ADCs

1 (20 x 10 bit), 1 (20 x 12 bit)

Length

9mm

Number of Ethernet Channels

0

Pulse Width Modulation

1 (24 Channel)

Program Memory Type

Flash

The Microchip PIC32MM0256GPM064 32-bit flash microcontroller has USB and ECC memory up to 256KB. It operates on 2V to 3.6V voltage range. This microcontroller has 256Kbytes program memory and 32KBytes data memory.

0.65 μA Sleep current for RAM Retention Regulator mode and 5 μA for Regulator Standby mode
On-Chip 1.8V Voltage Regulator (VREG)
On-Chip Ultra Low-Power Retention Regulator
microAptiv™ UC 32-Bit Core with 5-Stage Pipeline
microMIPS™ Instruction Set for 35% Smaller Code and 98% Performance compared to MIPS32 Instructions
1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance
3.17 CoreMark®/MHz (79 CoreMark) Performance
16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path
Two Sets of 32 Core Register Files (32-bit) to Reduce Interrupt Latency
Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply
64-Bit, Zero Wait State Flash with ECC to Maximize Endurance/Retention
Up to 32K SRAM Memory
Multiple Interrupt Vectors with Individually Programmable Priority
Fail-Safe Clock Monitor mode
Configurable Watchdog Timer with On-Chip, Low-Power RC Oscillator
Programmable Code Protection
Atomic Set, Clear and Invert Operation on Select Peripheral Registers
High-Current Sink/Source
Independent, Low-Power 32 kHz Timer Oscillator
Reference Clock Output (REFO)
Four Configurable Logic Cells (CLCs) with Internal Connections to Select Peripherals and PPS
Four-Channel Hardware DMA with Automatic Data Size Detection and CRC Engine
Sleep mode operation
Low-voltage boost for input
Band gap reference input feature
Windowed threshold compare feature
Brown-out Reset (BOR)