Infineon, 32bit ARM Cortex M0, PSoC 4200 Microcontroller, 48MHz, 32 kB Flash, 28-Pin SSOP

The Cypress Semiconductor PSoC 4 (Programmable Embedded System-on-Chip) family contain an ARM Cortex-M0 processor both product families 4100 and the 4200 platform architecture feature a combination of a microcontroller with op amps with Comparator mode, digital programmable logic, A/D converter as well as communication and timing devices. In the PSoC4 platform the controllers are compatible with each other for designing and new applications.

32-bit MCU Sub-system
24 MHz ARM Cortex-M0 CPU with single-cycle multiply (PSoC 4100 Family)
48 MHz ARM Cortex-M0 CPU with single cycle multiply (PSoC 4200 family)
Up to 32 kB of flash with Read Accelerator
Up to 4 kB of SRAM /SRAM+
Compatible with members of the PSoC 4 platform

32-bit MCU Sub-system
48-MHz ARM Cortex-M0 CPU with single cycle multiply
Up to 32 kB of flash with Read Accelerator
Up to 4 kB of SRAM
Programmable Analogue
Two Op Amps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes, and ADC input buffering capability
12-bit, 1-Msps SAR ADC with differential and single-ended modes, Channel Sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
Two low-power comparators that operate in Deep Sleep mode
Programmable Digital
Four programmable logic blocks called universal digital blocks,(UDBs), each with 8 Macro cells and data path
Cypress-provided peripheral component library, user-defined state machines, and Verilog input
Low Power 1.71-V to 5.5-V Operation
20-nA Stop Mode with GPIO pin wakeup
Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs
Capacitive Sensing
Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and water tolerance
Cypress-supplied software component makes capacitive sensing design easy
Automatic hardware tuning (SmartSense™)
Segment LCD Drive
LCD drive supported on all pins (common or segment)
Operates in Deep Sleep mode with 4 bits per pin memory