Renesas Electronics 9DB803DGILF, LVDS Buffer 8 TTL Buffer, 20-Pin TSSOP
- RS Stock No.:
- 217-7934
- Mfr. Part No.:
- 9DB803DGILF
- Brand:
- Renesas Electronics
Bulk discount available
Subtotal (1 tube of 39 units)*
£152.997
(exc. VAT)
£183.612
(inc. VAT)
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Units | Per unit | Per Tube* |
|---|---|---|
| 39 - 78 | £3.923 | £153.00 |
| 117 - 234 | £3.393 | £132.33 |
| 273 - 468 | £3.221 | £125.62 |
| 507 - 975 | £2.891 | £112.75 |
| 1014 + | £2.432 | £94.85 |
*price indicative
- RS Stock No.:
- 217-7934
- Mfr. Part No.:
- 9DB803DGILF
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Number of Drivers | 8 | |
| Input Type | TTL | |
| Output Type | Buffer | |
| Number of Elements per Chip | 2 | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Number of Drivers 8 | ||
Input Type TTL | ||
Output Type Buffer | ||
Number of Elements per Chip 2 | ||
Package Type TSSOP | ||
Pin Count 20 | ||
The Renesas Electronics 9DB803 is compatible with the Intel DB800v2 Differential Buffer Specification. This buffer provides 8 PCI Express Gen2 clocks. The 9DB803 is driven by a differential output pair from a CK410B+, CK505 or CK509B main clock generator.
8 - 0.7 V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
50-100 MHz operation in PLL mode
50-400 MHz operation in Bypass mode
Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% centre spread.
Supports undriven differential outputs in PD# and SRC_STOP# modes for power management.
Outputs cycle-cycle jitter < 50 ps
Outputs skew: 50 ps
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Phase jitter: PCIe Gen2 < 3.0/3.1 ps rms
48-pin SSOP/TSSOP package
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
50-100 MHz operation in PLL mode
50-400 MHz operation in Bypass mode
Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% centre spread.
Supports undriven differential outputs in PD# and SRC_STOP# modes for power management.
Outputs cycle-cycle jitter < 50 ps
Outputs skew: 50 ps
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Phase jitter: PCIe Gen2 < 3.0/3.1 ps rms
48-pin SSOP/TSSOP package