Nexperia 74HCT573D,652 8bit-Bit Latch, Transparent D Type, 3 State, 20-Pin SOIC
- RS Stock No.:
- 124-2269
- Mfr. Part No.:
- 74HCT573D,652
- Brand:
- Nexperia
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- RS Stock No.:
- 124-2269
- Mfr. Part No.:
- 74HCT573D,652
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | HCT | |
| Latch Mode | Transparent | |
| Latching Element | D Type | |
| Number of Bits | 8bit | |
| Output Type | 3 State | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SOIC | |
| Pin Count | 20 | |
| Dimensions | 13 x 7.6 x 2.45mm | |
| Height | 2.45mm | |
| Length | 13mm | |
| Maximum Operating Temperature | +125 °C | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Minimum Operating Temperature | -40 °C | |
| Width | 7.6mm | |
Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family HCT | ||
Latch Mode Transparent | ||
Latching Element D Type | ||
Number of Bits 8bit | ||
Output Type 3 State | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type SOIC | ||
Pin Count 20 | ||
Dimensions 13 x 7.6 x 2.45mm | ||
Height 2.45mm | ||
Length 13mm | ||
Maximum Operating Temperature +125 °C | ||
Maximum Operating Supply Voltage 5.5 V | ||
Minimum Operating Supply Voltage 4.5 V | ||
Minimum Operating Temperature -40 °C | ||
Width 7.6mm | ||
- COO (Country of Origin):
- TH
74HCT Family Flip-Flops & Latches, Nexperia
High-Speed CMOS Logic
Operating Voltage 4.5 to 5.5 V
Compatibility: Input TTL, Output CMOS
Operating Voltage 4.5 to 5.5 V
Compatibility: Input TTL, Output CMOS
The 74HC573, 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
74HCT Family
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