Nexperia 74HCT573D,652 8-Bit Latch, Transparent, 3 State, 20-Pin SOIC
- RS Stock No.:
- 124-2269
- Mfr. Part No.:
- 74HCT573D,652
- Brand:
- Nexperia
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- RS Stock No.:
- 124-2269
- Mfr. Part No.:
- 74HCT573D,652
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Product Type | Latch | |
| Logic Family | HCT | |
| Logic Function | D Type | |
| Latch Mode | Transparent | |
| Number of Bits | 8 | |
| Number of Channels | 1 | |
| Output Type | 3 State | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 4.5V | |
| Package Type | SOIC | |
| Maximum Supply Voltage | 5.5V | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 45ns | |
| Maximum Operating Temperature | 125°C | |
| Width | 7.6 mm | |
| Height | 2.45mm | |
| Standards/Approvals | JEDEC No. 7A | |
| Length | 13mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Product Type Latch | ||
Logic Family HCT | ||
Logic Function D Type | ||
Latch Mode Transparent | ||
Number of Bits 8 | ||
Number of Channels 1 | ||
Output Type 3 State | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 4.5V | ||
Package Type SOIC | ||
Maximum Supply Voltage 5.5V | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 45ns | ||
Maximum Operating Temperature 125°C | ||
Width 7.6 mm | ||
Height 2.45mm | ||
Standards/Approvals JEDEC No. 7A | ||
Length 13mm | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TH
The 74HC573, 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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