onsemi MC74AC377DWG D Type Flip Flop IC, 20-Pin SOIC
- RS Stock No.:
- 186-9315
- Mfr. Part No.:
- MC74AC377DWG
- Brand:
- onsemi
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 186-9315
- Mfr. Part No.:
- MC74AC377DWG
- Brand:
- onsemi
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | onsemi | |
| Logic Family | AC | |
| Logic Function | D Type | |
| Input Type | TTL | |
| Mounting Type | Surface Mount | |
| Package Type | SOIC | |
| Pin Count | 20 | |
| Set/Reset | Master Reset | |
| Number of Elements per Chip | 1 | |
| Maximum Propagation Delay Time @ Maximum CL | 14 ns @ 50 pF | |
| Maximum Operating Supply Voltage | 6 V | |
| Dimensions | 12.95 x 7.6 x 2.4mm | |
| Width | 7.6mm | |
| Height | 2.4mm | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Temperature | +85 °C | |
| Propagation Delay Test Condition | 50pF | |
| Length | 12.95mm | |
| Minimum Operating Supply Voltage | 2 V | |
| Select all | ||
|---|---|---|
Brand onsemi | ||
Logic Family AC | ||
Logic Function D Type | ||
Input Type TTL | ||
Mounting Type Surface Mount | ||
Package Type SOIC | ||
Pin Count 20 | ||
Set/Reset Master Reset | ||
Number of Elements per Chip 1 | ||
Maximum Propagation Delay Time @ Maximum CL 14 ns @ 50 pF | ||
Maximum Operating Supply Voltage 6 V | ||
Dimensions 12.95 x 7.6 x 2.4mm | ||
Width 7.6mm | ||
Height 2.4mm | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Temperature +85 °C | ||
Propagation Delay Test Condition 50pF | ||
Length 12.95mm | ||
Minimum Operating Supply Voltage 2 V | ||
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
ACT377 Has TTL Compatible Inputs
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
ACT377 Has TTL Compatible Inputs
