Nexperia 74LVC1G175GW,125 1 Flip Flop IC 74LVC, Single Ended, 6-Pin SC-88
- RS Stock No.:
- 170-5470
- Mfr. Part No.:
- 74LVC1G175GW,125
- Brand:
- Nexperia
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Units | Per unit | Per Pack* |
|---|---|---|
| 100 - 200 | £0.05 | £5.00 |
| 300 - 500 | £0.048 | £4.80 |
| 600 - 1100 | £0.045 | £4.50 |
| 1200 - 2400 | £0.038 | £3.80 |
| 2500 + | £0.036 | £3.60 |
*price indicative
- RS Stock No.:
- 170-5470
- Mfr. Part No.:
- 74LVC1G175GW,125
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | Single Ended | |
| Clock Frequency | 200MHz | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SC-88 | |
| Minimum Supply Voltage | 1.65V | |
| Maximum Supply Voltage | 5.5V | |
| Pin Count | 6 | |
| Maximum Propagation Delay Time @ CL | 5.5ns | |
| Minimum Operating Temperature | -40°C | |
| Trigger Type | Positive Edge | |
| Flip-Flop Type | D Flip-Flop | |
| Maximum Operating Temperature | 125°C | |
| Number of Elements per Chip | 1 | |
| Standards/Approvals | No | |
| Length | 2.2mm | |
| Height | 1mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74LVC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type Single Ended | ||
Clock Frequency 200MHz | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SC-88 | ||
Minimum Supply Voltage 1.65V | ||
Maximum Supply Voltage 5.5V | ||
Pin Count 6 | ||
Maximum Propagation Delay Time @ CL 5.5ns | ||
Minimum Operating Temperature -40°C | ||
Trigger Type Positive Edge | ||
Flip-Flop Type D Flip-Flop | ||
Maximum Operating Temperature 125°C | ||
Number of Elements per Chip 1 | ||
Standards/Approvals No | ||
Length 2.2mm | ||
Height 1mm | ||
Automotive Standard No | ||
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, Master reset (MR) input, and Q output. The Master reset (MR) is an asynchronous Active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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