Nexperia 74AUP1G74DC,125 1 Flip Flop AUP, CMOS, Push Pull, 8-Pin VSSOP-8
- RS Stock No.:
- 625-406
- Mfr. Part No.:
- 74AUP1G74DC,125
- Brand:
- Nexperia
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Units | Per unit |
|---|---|
| 1 - 24 | £0.27 |
| 25 + | £0.25 |
*price indicative
- RS Stock No.:
- 625-406
- Mfr. Part No.:
- 74AUP1G74DC,125
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Product Type | Flip Flop | |
| Logic Family | AUP | |
| Input Type | Single Ended | |
| Output Type | CMOS, Push Pull | |
| Clock Frequency | 619MHz | |
| Polarity | Positive | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 0.8V | |
| Package Type | VSSOP-8 | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 8 | |
| Flip-Flop Type | D Flip-Flop | |
| Trigger Type | Positive Edge | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Number of Elements per Chip | 1 | |
| Height | 0.32mm | |
| Length | 1mm | |
| Series | 74AUP1G74 | |
| Standards/Approvals | JS-002, JESD8-11, JESD8-5, JESD8-7, JESD8C, ESD:ANSI/ESDA/JEDEC JS-001, JEDEC:JESD8-12 | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Product Type Flip Flop | ||
Logic Family AUP | ||
Input Type Single Ended | ||
Output Type CMOS, Push Pull | ||
Clock Frequency 619MHz | ||
Polarity Positive | ||
Mount Type Surface | ||
Minimum Supply Voltage 0.8V | ||
Package Type VSSOP-8 | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 8 | ||
Flip-Flop Type D Flip-Flop | ||
Trigger Type Positive Edge | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Number of Elements per Chip 1 | ||
Height 0.32mm | ||
Length 1mm | ||
Series 74AUP1G74 | ||
Standards/Approvals JS-002, JESD8-11, JESD8-5, JESD8-7, JESD8C, ESD:ANSI/ESDA/JEDEC JS-001, JEDEC:JESD8-12 | ||
Automotive Standard No | ||
The Nexperia Single positive edge-triggered D-type flip-flop is designed with individual data (D), clock (CP), set (SD), and reset (RD) inputs, along with complementary Q and Q̅ outputs. Data on the D input is stored on the low-to-high transition of the clock, provided setup and hold time requirements are met, and appears at the Q output.
Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
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