Nexperia 74HCT138D,653, Decoder, 16-Pin SO16
- RS Stock No.:
- 170-5460
- Mfr. Part No.:
- 74HCT138D,653
- Brand:
- Nexperia
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Units | Per unit | Per Pack* |
|---|---|---|
| 50 - 200 | £0.313 | £15.65 |
| 250 - 950 | £0.169 | £8.45 |
| 1000 - 2450 | £0.132 | £6.60 |
| 2500 + | £0.114 | £5.70 |
*price indicative
- RS Stock No.:
- 170-5460
- Mfr. Part No.:
- 74HCT138D,653
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Mounting Type | Surface Mount | |
| Package Type | SO16 | |
| Pin Count | 16 | |
| Dimensions | 6.4 x 5.4 x 1.8mm | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Maximum Operating Temperature | +125 °C | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Minimum Operating Temperature | -40 °C | |
Select all | ||
|---|---|---|
Brand Nexperia | ||
Mounting Type Surface Mount | ||
Package Type SO16 | ||
Pin Count 16 | ||
Dimensions 6.4 x 5.4 x 1.8mm | ||
Maximum Operating Supply Voltage 5.5 V | ||
Maximum Operating Temperature +125 °C | ||
Minimum Operating Supply Voltage 4.5 V | ||
Minimum Operating Temperature -40 °C | ||
- COO (Country of Origin):
- TH
The 74HC138, 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four ’138’ ICs and one inverter. The ’138’ can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes.
Multiple input enable for easy expansion or independent controls
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
Can be cascaded
Key applications
Selection of memory banks and peripherals
I/O expansion
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
Can be cascaded
Key applications
Selection of memory banks and peripherals
I/O expansion