Nexperia 74HC238PW,118, Decoder, 16-Pin TSSOP
- RS Stock No.:
- 170-4872
- Mfr. Part No.:
- 74HC238PW,118
- Brand:
- Nexperia
Subtotal (1 reel of 2500 units)*
£385.00
(exc. VAT)
£462.50
(inc. VAT)
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- Shipping from 01 May 2026
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Units | Per unit | Per Reel* |
---|---|---|
2500 + | £0.154 | £385.00 |
*price indicative
- RS Stock No.:
- 170-4872
- Mfr. Part No.:
- 74HC238PW,118
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Nexperia | |
Mounting Type | Surface Mount | |
Package Type | TSSOP | |
Pin Count | 16 | |
Dimensions | 5.1 x 4.5 x 0.95mm | |
Maximum Operating Supply Voltage | 6 V | |
Maximum Operating Temperature | +125 °C | |
Minimum Operating Temperature | -40 °C | |
Minimum Operating Supply Voltage | 2 V | |
Select all | ||
---|---|---|
Brand Nexperia | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Dimensions 5.1 x 4.5 x 0.95mm | ||
Maximum Operating Supply Voltage 6 V | ||
Maximum Operating Temperature +125 °C | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 2 V | ||
- COO (Country of Origin):
- TH
The 74HC238: 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter. The '238 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes.
Multiple input enable for easy expansion or independent controls
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
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