Nexperia 74LVC138APW,118, Decoder, 16-Pin TSSOP
- RS Stock No.:
- 170-4837
- Mfr. Part No.:
- 74LVC138APW,118
- Brand:
- Nexperia
Subtotal (1 reel of 2500 units)*
£285.00
(exc. VAT)
£342.50
(inc. VAT)
FREE delivery for orders over £50.00
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- Shipping from 01 May 2026
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Units | Per unit | Per Reel* |
---|---|---|
2500 + | £0.114 | £285.00 |
*price indicative
- RS Stock No.:
- 170-4837
- Mfr. Part No.:
- 74LVC138APW,118
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Nexperia | |
Mounting Type | Surface Mount | |
Package Type | TSSOP | |
Pin Count | 16 | |
Dimensions | 5.1 x 4.5 x 0.95mm | |
Maximum Operating Supply Voltage | 3.6 V | |
Maximum Operating Temperature | +125 °C | |
Minimum Operating Temperature | -40 °C | |
Minimum Operating Supply Voltage | 1.2 V | |
Select all | ||
---|---|---|
Brand Nexperia | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Dimensions 5.1 x 4.5 x 0.95mm | ||
Maximum Operating Supply Voltage 3.6 V | ||
Maximum Operating Temperature +125 °C | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 1.2 V | ||
- COO (Country of Origin):
- CN
The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74LVC138A devices and one inverter.
Multiple input enable for easy expansion or independent controls
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
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