The Renesas Electronics RC32504A universal frequency translator is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. It can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a Synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications.

Jitter below 100fs RMS (10kHz to 20MHz)
Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
Reference monitor qualifies/disqualifies input clock
Programmable status output
Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
4 x 4 mm 24-QFN package
4 differential/8 LVCMOS outputs
Output Enable input with programmable effect