8SLVP1208ANBGI, Clock Buffer LVPECL, 4-Input, 28-Pin LFCSP
- RS Stock No.:
- 216-6232
- Mfr. Part No.:
- 8SLVP1208ANBGI
- Brand:
- Renesas Electronics
Subtotal (1 tray of 490 units)*
£2,041.34
(exc. VAT)
£2,449.51
(inc. VAT)
FREE delivery for orders over £50.00
Temporarily out of stock
- 999,999,840 unit(s) shipping from 23 January 2026
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Units | Per unit | Per Tray* |
|---|---|---|
| 490 + | £4.166 | £2,041.34 |
*price indicative
- RS Stock No.:
- 216-6232
- Mfr. Part No.:
- 8SLVP1208ANBGI
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Family | LVPECL | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVPECL | |
| Number of Clock Inputs | 4 | |
| Package Type | LFCSP | |
| Pin Count | 28 | |
Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Family LVPECL | ||
Logic Function Clock Buffer | ||
Input Signal Type LVPECL | ||
Number of Clock Inputs 4 | ||
Package Type LFCSP | ||
Pin Count 28 | ||
The Renesas Electronics 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability.
Eight low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)