Microchip ZL30634LDG1 Clock Driver & Distribution, 64-Pin 20 VQFN
- RS Stock No.:
- 428-144
- Mfr. Part No.:
- ZL30634LDG1
- Brand:
- Microchip
Subtotal (1 tray of 260 units)*
£21,628.10
(exc. VAT)
£25,953.72
(inc. VAT)
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- Shipping from 10 April 2026
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Units | Per unit | Per Tray* |
|---|---|---|
| 260 + | £83.185 | £21,628.10 |
*price indicative
- RS Stock No.:
- 428-144
- Mfr. Part No.:
- ZL30634LDG1
- Brand:
- Microchip
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Product Type | Clock Driver & Distribution | |
| Mount Type | Surface | |
| Package Type | VQFN | |
| Pin Count | 64 | |
| Minimum Supply Voltage | 1.8V | |
| Maximum Supply Voltage | 3.3V | |
| Width | 9 mm | |
| Series | ZL30631 - ZL30635 | |
| Standards/Approvals | G.8262.1, PCIe, GR-253, Telcordia GR-1244, G.813, G.812, ITU-T G.8262, JESD204B | |
| Maximum Output Frequency | 750MHz | |
| Automotive Standard | No | |
| Number of Outputs | 20 | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Product Type Clock Driver & Distribution | ||
Mount Type Surface | ||
Package Type VQFN | ||
Pin Count 64 | ||
Minimum Supply Voltage 1.8V | ||
Maximum Supply Voltage 3.3V | ||
Width 9 mm | ||
Series ZL30631 - ZL30635 | ||
Standards/Approvals G.8262.1, PCIe, GR-253, Telcordia GR-1244, G.813, G.812, ITU-T G.8262, JESD204B | ||
Maximum Output Frequency 750MHz | ||
Automotive Standard No | ||
Number of Outputs 20 | ||
- COO (Country of Origin):
- MY
The Microchip PTP & SyncE Network Synchronizers support up to 4 channel and 10 outputs, with 5 GPIO pins that offer various behaviors. Each REF can function as a GPI, while each OUT can act as a GPO. They feature an SPI or I2C processor interface and operate with 1.8V and 3.3V core VDD voltages. Additionally, they come with easy-to-use evaluation and programming software.
Automatic self-configuration from internal Flash with 7 configurations
NCO behavior in each DPLL and synthesizer
No external VCXO or loop filter required
Easy to configure design