The Renesas Electronics high performance, low skew clock buffer that operates up to 200MHz. Two banks of five outputs each provide low skew copies of CLK. Through the use of control pins 1G and 2G, the outputs of banks 1Y(0:4) and 2Y(0:4) can be placed in a low state regardless of CLK input. The device operates in 2.5V and 3.3V environments. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. The IDT5V2310 is characterized for operation from -40°C to +85°C.

High performance 1:10 clock driver for general purpose applications
Pin-to-pin skew < 100 ps
VDD range is 2.3 V to 3.6 V
Output enable glitch suppression
Distributes one clock input to two banks of five outputs
25 Ω on-chip series dampening resistors
Available in TSSOP package