The Renesas Electronics high performance, low skew clock buffer that operates up to 200 MHz. One bank of five outputs provides low skew copies of CLK. Through the use of control pin G, the outputs of bank Y(0:4) can be placed in a low state regardless of CLK input. The device operates in 2.5 V and 3.3 V environments. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. It is is characterized for operation from -40°C to +85°C.

High performance 1:5 clock driver for general purpose applications
Operates up to 170 MHz at VDD is 2.5 V
Operates up to 200 MHz at VDD is 3.3 V
Pin-to-pin skew < 75 ps at 3.3 V operation
VDD range is 2.3 V to 3.6 V
Output enable glitch suppression
Available in TSSOP and VFQFPN packages