The Cypress Semiconductor CY7C1412KV18 series are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

333 MHz clock for high bandwidth
Two-word burst on all accesses
Double data rate (DDR) Interfaces on both read and write ports at 333 MHz
Two input clocks for precise DDR timing
Two input clocks for output data to minimize clock skew and flight time mismatches
Echo clocks simplify data capture in high speed systems
Single multiplexed address input bus latches address inputs for both read and write ports