The Cypress Semiconductor CY7C1371KV33 are 3.3 V, 512K ´ 36 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. It is equipped with the advanced no bus latency logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT devices
Internally self-timed output buffer control to eliminate the need to use OE
Registered inputs for flow through operation
Byte write capability