Cypress Semiconductor SRAM Memory Chip, CY7C1049GN30-10ZSXI- 4Mbit
- RS Stock No.:
- 181-7450
- Mfr. Part No.:
- CY7C1049GN30-10ZSXI
- Brand:
- Cypress Semiconductor
Subtotal (1 tray of 135 units)*
£619.515
(exc. VAT)
£743.445
(inc. VAT)
Stock information currently inaccessible - Please check back later
Units | Per unit | Per Tray* |
|---|---|---|
| 135 + | £4.589 | £619.52 |
*price indicative
- RS Stock No.:
- 181-7450
- Mfr. Part No.:
- CY7C1049GN30-10ZSXI
- Brand:
- Cypress Semiconductor
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Cypress Semiconductor | |
| Memory Size | 4Mbit | |
| Organisation | 512k x 8 bit | |
| Number of Words | 512k | |
| Number of Bits per Word | 8bit | |
| Maximum Random Access Time | 10ns | |
| Timing Type | Asynchronous | |
| Mounting Type | Surface Mount | |
| Package Type | TSOP | |
| Pin Count | 44 | |
| Dimensions | 18.51 x 10.26 x 1.04mm | |
| Height | 1.04mm | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Minimum Operating Supply Voltage | 2.2 V | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Temperature | +85 °C | |
| Length | 18.51mm | |
| Width | 10.26mm | |
| Select all | ||
|---|---|---|
Brand Cypress Semiconductor | ||
Memory Size 4Mbit | ||
Organisation 512k x 8 bit | ||
Number of Words 512k | ||
Number of Bits per Word 8bit | ||
Maximum Random Access Time 10ns | ||
Timing Type Asynchronous | ||
Mounting Type Surface Mount | ||
Package Type TSOP | ||
Pin Count 44 | ||
Dimensions 18.51 x 10.26 x 1.04mm | ||
Height 1.04mm | ||
Maximum Operating Supply Voltage 3.6 V | ||
Minimum Operating Supply Voltage 2.2 V | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Temperature +85 °C | ||
Length 18.51mm | ||
Width 10.26mm | ||
CY7C1049GN is a high-performance CMOS fast static RAM device organized as 512K words by 8-bits. Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O0through I/O7 and address on A0 through A18 pins. Data reads are performed by asserting the Chip Enable (CE) and Output Enable (OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O7). All I/Os (I/O0 through I/O7) are placed in a high-impedance state=during the following events:The device is deselected (CE HIGH) The control signal OE is de-asserted
High speed
tAA = 10 ns
Low active and standby currents
Active current: ICC = 38 mA typical
Standby current: ISB2 = 6 mA typical
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
1.0 V data retention
TTL-compatible inputs and outputs
Pb-free 36-pin SOJ and 44-pin TSOP II packages
tAA = 10 ns
Low active and standby currents
Active current: ICC = 38 mA typical
Standby current: ISB2 = 6 mA typical
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
1.0 V data retention
TTL-compatible inputs and outputs
Pb-free 36-pin SOJ and 44-pin TSOP II packages