- RS Stock No.:
- 181-8347
- Mfr. Part No.:
- S27KS0641DPBHI020
- Brand:
- Infineon
Available to back order for despatch when stock is available
Added
Price Each (In a Pack of 3)
£4.017
(exc. VAT)
£4.82
(inc. VAT)
Units | Per unit | Per Pack* |
3 - 27 | £4.017 | £12.051 |
30 - 72 | £3.837 | £11.511 |
75 - 147 | £3.817 | £11.451 |
150 - 297 | £3.78 | £11.34 |
300 + | £3.737 | £11.211 |
*price indicative |
- RS Stock No.:
- 181-8347
- Mfr. Part No.:
- S27KS0641DPBHI020
- Brand:
- Infineon
Technical Reference
Legislation and Compliance
Product Details
3.0 V I/O, 11 bus signals
Single ended clock (CK)
1.8 V I/O, 12 bus signals
Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
Bidirectional Data Strobe / Mask
Output at the start of all transactions to indicate refresh latency
Output during read transactions as Read Data Strobe
Input during write transactions as Write Data Mask
RWDS DCARS Timing
During read transactions RWDS is offset by a second clock, phase shifted from CK
The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye
Up to 333 MBps
Double-Data Rate (DDR) - two data transfers per clock
166 MHz clock rate (333 MBps) at 1.8 V VCC
100 MHz clock rate (200 MBps) at 3.0 V VCC
Sequential burst transactions
Configurable Burst Characteristics
Wrapped burst lengths:
16 bytes (8 clocks)
32 bytes (16 clocks)
64 bytes (32 clocks)
128 bytes (64 clocks)
Linear burst
Hybrid option - one wrapped burst followed by linear burst
Wrapped or linear burst type selected in each transaction
Configurable output drive strength
Low Power Modes
Deep Power Down
Package
24-ball FBGA
Single ended clock (CK)
1.8 V I/O, 12 bus signals
Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
Bidirectional Data Strobe / Mask
Output at the start of all transactions to indicate refresh latency
Output during read transactions as Read Data Strobe
Input during write transactions as Write Data Mask
RWDS DCARS Timing
During read transactions RWDS is offset by a second clock, phase shifted from CK
The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye
Up to 333 MBps
Double-Data Rate (DDR) - two data transfers per clock
166 MHz clock rate (333 MBps) at 1.8 V VCC
100 MHz clock rate (200 MBps) at 3.0 V VCC
Sequential burst transactions
Configurable Burst Characteristics
Wrapped burst lengths:
16 bytes (8 clocks)
32 bytes (16 clocks)
64 bytes (32 clocks)
128 bytes (64 clocks)
Linear burst
Hybrid option - one wrapped burst followed by linear burst
Wrapped or linear burst type selected in each transaction
Configurable output drive strength
Low Power Modes
Deep Power Down
Package
24-ball FBGA
Specifications
Attribute | Value |
---|---|
Memory Size | 64Mbit |
Organisation | 8M x 8 bit |
Data Rate | 333Mbit/s |
Data Bus Width | 8bit |
Number of Bits per Word | 8bit |
Maximum Random Access Time | 36ns |
Number of Words | 8M |
Mounting Type | Surface Mount |
Package Type | FBGA |
Pin Count | 24 |
Dimensions | 8 x 6 x 0.8mm |
Height | 0.8mm |
Length | 8mm |
Minimum Operating Temperature | -40 °C |
Width | 6mm |
Maximum Operating Supply Voltage | 1.95 V |
Maximum Operating Temperature | +85 °C |
Minimum Operating Supply Voltage | 1.7 V |
Related links
- Alliance Memory AS4C64M16D2A-25BIN 400MHz 84-Pin FBGA
- Infineon S27KS0643GABHV020 200MHz 24-Pin FBGA
- Alliance Memory AS4C4M16SA-6TIN 200MHz 54-Pin TSOP
- Alliance Memory AS4C4M16SA-7TCN 200MHz 54-Pin TSOP
- Alliance Memory AS4C4M16SA-7BCN 200MHz 54-Pin FBGA
- Winbond W9864G6KH-6I 166MHz 54-Pin TSOP
- ISSI IS42S16400J-7TLI 143MHz 54-Pin TSOP
- Infineon S27KL0642DPBHI020 400Mbps, 24-Pin 24-ball FBGA